// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// -----------------------------------------------------------------------------
// Author 		: HiDark 1173296519@qq.com
// File   		: SRAM_SP_4KX32.v
// Create 		: 2023-12-24 13:04:00
// Description	: Single port sram 8bit,4096s behavioral model
// Editor 		: tab size (4)
// -----------------------------------------------------------------------------
module SRAM_SP_4KX32 #(  
    parameter  ADDR_WIDTH = 12,
    parameter  DATA_WIDTH = 32,    
    parameter  DATA_DEPTH = 4096  
)(
    // Inputs
    input                           clk,
    input                           wen,
    input                           csn,
    input       [ADDR_WIDTH-1:0]    addr,
    input       [DATA_WIDTH-1:0]    din,
    // Outputs
    output  reg [DATA_WIDTH-1:0]    dout
);

reg [DATA_WIDTH-1:0] ram [0:DATA_DEPTH-1];
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
always @(posedge clk) begin
    if(wen == 1'b1 && csn == 1'b0)
        dout      <= ram[addr];
    else
        dout      <= {DATA_WIDTH{1'bz}};
end

//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
always @(posedge clk) begin
    if(wen == 1'b0 && csn == 1'b0)
        ram[addr] <= din;
end

endmodule